Semiconductor memory device having a gate electrode and a diffusion layer and a manufacturing method thereof

ABSTRACT

A semiconductor memory device having a gate electrode and a diffusion layer, comprising a plurality of memory cells each of which including the gate electrode and the diffusion layers; a first contact layer connected to one of the diffusion layer of the memory cell; a second contact layer connected to the first contact layer; a bit line connected to the second contact layer; and a conductive layer connected to at least two of the diffusion layers that are other than the diffusion layer connected to the first contact layer, at least two of the diffusion layers being arranged in a direction vertical to the bit line, a height of the conductive layer substantially being same as a height of the first contact layer.

A semiconductor memory device having a gate electrode and a diffusionlayer and a manufacturing method thereof.

CROSS-REFERENCE TO RELATED APPLICATION

This application is based upon and claims the benefit of priority fromthe prior Japanese Patent Application No. 2002-314627, filed Oct. 29,2002, the entire contents of which are incorporated herein by reference.

BACKGROUND OF THE INVENTION

1. Field of the Invention

This present invention relates to a semiconductor memory device and amanufacturing method thereof, for example, a nonvolatile semiconductormemory device and its manufacturing method that are suitable for highintegrality.

2. Description of the Related Art

A top view of a conventional NOR type non volatile semiconductor memorydevice is shown in FIG. 6. As shown in FIG. 6, a plurality of elementregion (ER) are arranged in a horizontal direction of the FIG. 6. Eachof the element regions is electrically separated from each other byelement isolation regions STI (Shallow Trench Isolation). A plurality ofword lines WL1 portions of which are used as gate electrodes arearranged in a vertical direction of FIG. 6 so as to intersect each ofthe element regions.

Drain contacts 102 a are arranged between two word lines WL1 andconnects between a drain region formed on a upper surface of thesemiconductor substrate 100 and a bit line 115. The drain contact 102 ais used in common at memory cells that are arranged at both sides of thedrain contact 102 a.

A source line 103 is arranged in parallel to the word line WL1 at anopposite side where the drain contacts 102 a are not formed. The sourceline 103 is connected to source regions that are formed on an uppersurface of the semiconductor substrate 100. A source contact 102 b isformed on the source line 103. The source contact 102 b is connectedbetween the source line 103 and another line (not shown) that is formedin a same layer as the bit line 115.

FIGS. 4 and 5 show cross sectional views of the A-A and the B-B shown inFIG. 6 respectively. As shown in FIG. 5, a plurality of elementisolation regions (STI) are formed on an upper surface of thesemiconductor substrate 100, thereby forming a plurality of elementregions each of which is arranged between the two element isolationregions. A word line WL1 is formed so as to intersect each of theelement regions.

As shown in FIGS. 4 and 5, the word line WL1 is formed on a siliconoxide layer 101 (a first gate insulating film) that is formed on thesemiconductor substrate 100. The word line WL1 also includes a polycrystalline silicon layer 104 that is used as a first floating gate, apoly crystalline silicon layer 105 that is used as a second floatinggate, an ONO layer 106 that is used as a second gate insulating film, acontrol gate electrode comprised of a poly crystalline silicon layer 107and a tungsten silicon layer 108 (WSi), and a TEOS layer 109 that wasused as a mask layer to form a gate electrode.

A silicon nitride layer 110 is formed on the side surface of the wordline WL1. A silicon nitride layer 111 is formed to cover the siliconnitride layer 110. Silicon oxide layers 112 and 131 are formed tofulfill between gate electrodes covered by the silicon nitride layer111. And then, portions of the silicon oxide layers 112 and 131 areremoved and flatted by using a CMP method.

Conventionally, drain contacts 102 a and source line 103 are formed atdifferent manufacturing steps. First, the source line 103 is formed, andthen the drain contacts 102 a are formed. Details of the manufacturingstep are as follows.

Portions of a silicon oxide layer 101, a silicon nitride layer 111,silicon oxide layers 112 and 131 are removed to a direction vertical tothe element region and the element isolation region, and parallel to theword line WL1 by using a RIE method (Reactive Ion Etching), therebyforming a contact hole to reach source regions that are formed on anupper surface of the semiconductor substrate 100. And the, a metal layer114 b, for instance, tungsten layer W is formed in the contact hole,thereby forming a source line 103.

After that, a silicon oxide layer 113 that is used as an interlayerinsulating layer is formed and flatted by using a CMP (ChemicalMechanical Polishing) method. At positions where the source line 103 isnot formed, portions of a silicon oxide layer 101, a silicon nitridelayer 111, silicon oxide layers 112, 131, and 113 are removed so as toexpose upper surfaces of the silicon substrate 100 by using a RIEmethod, thereby forming contact holes. A metal layer 114 a, forinstance, tungsten W is then formed in the contact hole, thereby formingdrain contacts 102 a. After that, portion of the silicon oxide layer 112is removed so as to expose an upper surface of the source line 103 byusing a RIE method, thereby forming a contact hole. A metal layer 116,for instance, tungsten W is then formed in the contact hole, therebyforming a source contact 102 b that electrically connects between thesource line 103 and line layer (not shown).

It is noted that a conventional semiconductor memory devices with asource line structure are shown in following materials. IEDM98-975-978(Novel 0.44 μm² Ti-Salicide STI Cell Technology for High-Density NORFlash Memories and High Performance Embedded Application), Japanesepatent laid open Hei10-326896, Hei6-334156, Hei7-74325, Hei11-265947,2002-76147, Hei9-129854, and 2001-68571.

The conventional semiconductor memory device has a following problem. Inthe conventional semiconductor memory device, the drain contact 102 a isformed after the source line 103 and the silicon oxide layer 113 areformed. Therefore, it is necessary to form a contact hole with a depththat is total thickness of the source line 103 and the silicon oxidelayer 113, and fulfill the metal layer 114 a in the contact hole. Inthis result, an aspect ratio of the contact hole is higher and it isdifficult to fulfill the metal layer 114 a in the contact hole, therebyresulting in occurrence of voids and a poor conduction.

It is necessary to use different photo resist masks when a RIE method isachieved in order to form the source line 103 and the drain contact 102a. Furthermore, it is necessary to form a contact hole of the sourcecontact 102 b so as to connect between the source line 103 and aconductive line. In this result, the source contact 102 b may bedeviated from the source line 103, thereby resulting in a poorconduction.

SUMMARY OF INVENTION

A first aspect of the present invention is providing a semiconductormemory device having a gate electrode and a diffusion layer, comprisinga plurality of memory cells each of which including the gate electrodeand the diffusion layers; a first contact layer connected to one of thediffusion layer of the memory cell; a second contact layer connected tothe first contact layer; a bit line connected to the second contactlayer; and a conductive layer connected to at least two of the diffusionlayers that are other than the diffusion layer connected to the firstcontact layer, at least two of the diffusion layers being arranged in adirection vertical to the bit line, a height of the conductive layersubstantially being same as a height of the first contact layer.

A second aspect of the present invention is providing a semiconductormemory device having a gate electrode and a diffusion layer, comprisinga plurality of memory cells each of which including the gate electrodeand the diffusion layer; an insulating film formed above side and topsurfaces of the gate electrode of the semiconductor memory device; afirst interlayer insulating layer formed between the gate electrode ofthe semiconductor memory device; a first contact layer formed in thefirst interlayer insulating layer and connected to the diffusion layer;a second interlayer insulting layer formed on the first inter layerinsulating layer; a second contact layer formed in the second interlayerinsulating layer and connected to the first contact layer; a bit lineconnected to the second contact layer; and a conductive layer connectedto at least two of the diffusion layers that are other than thediffusion layer connected to the first contact layer, at least two ofthe diffusion layers being arranged in a direction vertical to the bitline, a height of the conductive layer substantially being same as aheight of the first contact layer.

A third aspect of the present invention is providing a method ofmanufacturing a semiconductor memory device having a gate electrode anda diffusion layer, comprising forming a plurality of memory cells eachof which including the gate electrode and the diffusion layer; forming afirst interlayer insulating film among the gate electrodes of theplurality of the memory cells; forming a first contact hole and a secondcontact hole, the first contact hole reaches one of the diffusion layersof the plurality of the memory cells and the second contact hole reachesat least two of the diffusion layers of the plurality of the memorycells; forming a first conductive layer in the first contact hole and asecond conductive layer in the second contact hole; forming a secondinterlayer insulating film on the first interlayer insulating film;forming a third contact hole in the second interlayer insulating film;forming a third conductive layer in the third contact hole, the thirdconductive layer connected to the first conductive layer; and forming abit line connected to the third conductive layer.

A fourth aspect of the present invention is providing a method ofmanufacturing a semiconductor memory device having a gate electrode anda diffusion layer, comprising forming a plurality of memory cells eachof which including the gate electrode and the diffusion layer; forming afirst interlayer insulating film among the gate electrodes of theplurality of the memory cells; removing portions of the first interlayerinsulating film and forming a first contact hole and a second contacthole, the first contact hole reaches one of the diffusion layers of theplurality of the memory cells and the second contact hole reaches atleast two of the diffusion layers of the plurality of the memory cells;forming a first conductive layer in the first contact hole and a secondconductive layer in the second contact hole; forming a second interlayerinsulating film on the first interlayer insulating film, the firstconductive layer, and the second conductive layer; removing a portion ofthe second interlayer insulting film and forming a third contact hole;forming a third conductive layer in the third contact hole, the thirdconductive layer connected to the first conductive layer; and forming abit line connected to the third conductive layer.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 shows a C-C cross sectional view of a non-volatile memory deviceassociated with a first embodiment of the present invention shown inFIG. 3.

FIG. 2 shows a D-D cross sectional view of the non-volatile memorydevice associated with the first embodiment of the present inventionshown in FIG. 3.

FIG. 3 shows a top view of the non-volatile memory device associatedwith the first embodiment of the present invention.

FIG. 4 shows a manufacturing step of the non-volatile memory deviceassociated with a first embodiment of the present invention.

FIG. 5 shows a manufacturing step of the non-volatile memory deviceassociated with the first embodiment of the present invention.

FIG. 6 shows a A-A cross sectional view of a conventional non-volatilememory device shown in FIG. 8.

FIG. 7 shows a A-A cross sectional view of a conventional non-volatilememory device shown in FIG. 8.

FIG. 8 shows a top view of a conventional non-volatile memory device.

FIG. 9 shows a diagram of a memory card in which a semiconductor memorydevice is arranged.

FIG. 10 shows a diagram of a memory card in which a semiconductor memorydevice and a controller are arranged.

FIG. 11 shows a diagram of a card holder to which a memory card isinserted.

FIG. 12 shows a diagram of a connecting apparatus, a board, and aconnecting wire.

FIG. 13 shows a diagram of a PC, a connecting apparatus, and aconnecting wire.

FIG. 14 shows a diagram of an IC chip including a semiconductor memorydevice, and an IC card on which the IC card is allocated.

FIG. 15 shows a schematic diagram of an IC card and an IC chip.

DETAILED DESCRIPTION OF THE INVENTION

Hereinafter, we will explain about an embodiment of the presentinvention with reference to drawings, specifically NOR type non-volatilememory device.

First Embodiment

A top view of a first embodiment of the present invention is shown inFIG. 3. A plurality of element regions are arranged in a paralleldirection in FIG. 3. Each of the element regions is electricallyseparated from each other by an element isolation region. A plurality ofword lines WL2 are arranged in a vertical direction in FIG. 3 so as tointersect each of the element regions.

A C-C cross sectional view in FIG. 3 is shown in FIG. 1 and a D-D crosssectional view in FIG. 3 is shown in FIG. 2. As shown in FIGS. 1 and 2,a drain contact 202 a that connects between a bit line 215 and a drainregion formed on an upper surface of a semiconductor substrate 200 isformed. The drain contact 202 a is used in common at memory cells thatare arranged at both sides of the drain contact 202 a. It is noted thatthe bit line 215 may be comprised of, for instance, one of a barriermetal Ti and a barrier metal TiN, a metal layer, and one of a barriermetal Ti and a barrier metal TiN.

A source line 203 that is parallel to the word lines WL2 is arranged andconnected to source regions 301 that are formed on upper surfaces of thesemiconductor substrate 200. A source contact 202 b is formed on thesource line 203 and connects between a conductive line (not shown) andthe source line 203.

As shown in FIG. 2, element isolation regions STI are formed on theupper surface of the semiconductor substrate 200, thereby resulting informing element regions ER each of which is electrically isolated by theelement isolation regions STI. The word lines WL2 are formed above theelement regions ER so as to intersect the element regions ER.

As shown in FIGS. 1 and 2, the word line WL2 is formed on a siliconoxide layer 201 (a first gate insulating film) that is formed on thesemiconductor substrate 200. The word line WL2 also includes a polycrystalline silicon layer 204 that is used as a first floating gate, apoly crystalline silicon layer 205 that is used as a second floatinggate, an ONO layer 206 that is used as a second gate insulating film, acontrol gate electrode comprised of a poly crystalline silicon layer 207and a tungsten silicon layer 208 (WSi), and a TEOS layer 209 that wasused as a mask layer to form a gate electrode.

Manufacturing steps will be explain with reference to FIGS. 4 and 5. Asshown in FIG. 4, the silicon oxide layer 201 is formed on thesemiconductor substrate 200. The poly crystalline silicon layer 204, asilicon nitride layer (not shown), and a silicon oxide layer (not shown)are formed on the silicon oxide layer 204. A resist layer is then formedon the silicon oxide layer (not shown) and is processed into a patternof a gate electrode by using a photolithography technique. Portions ofthe silicon nitride layer (not shown) and the silicon oxide layer (notshown) are removed by using a RIE method and the patterned photo resistlayer as a mask. And then he patterned resist layer is removed. Afterthat, portion of the poly crystalline silicon layer 204 is patterned byusing a RIE method and the patterned silicon oxide layer (not shown).

Portions of the silicon oxide layer 201 and the silicon substrate 200are removed by using a RIE method and the patterned poly crystallinesilicon layer 204 as a mask, thereby forming trench grooves of STI(Shallow Trench Isolation) in an upper surface of the silicon substrate200. After that, a silicon oxide layer (not shown) is formed on theupper surface of the silicon substrate 200 and a inner wall of thetrench grooves of the STI by using a thermal oxide method.

A silicon oxide layer (not shown) is formed in the trench grooves of theSTI so as to fulfill the trench grooves of the STI by using a HDP (HighDensity Plasma) method. The silicon oxide layer (not shown) is removedand flattened so as to expose an upper surface of the poly crystallinesilicon 204 by using a CMP (Chemical Mechanical Polish) method. Thesilicon nitride layer (not shown) that is formed on the silicon oxidelayer (not shown) is then removed by using a phosphorous acid process. Apoly crystalline silicon 205 to which phosphorus (P) is doped is formedby using a low pressure CVD method and is patterned into gate electrodesby using a RIE method.

An ONO layer 206, a P doped poly crystalline silicon 207, a WSi layer208, and a silicon oxide layer 209 are formed by using a low pressureCVD method. A patterned photo resist layer (not shown) is formed on thesilicon oxide layer 209 by using a photolithography technique. Portionsof he silicon oxide layer 209 are removed by using a RIE method and thepatterned photo resist layer as a mask.

Portions of the WSi layer 208, the poly crystalline silicon layer 207,the ONO layer 206, the poly crystalline silicon layers 205 and 204 areremoved by using a RIE method and the patterned silicon oxide layer 209as a mask, thereby forming the word lines WL2 (gate electrodes). Asilicon oxide layer 230 is then formed on the side and top surfaces ofeach of the word lines WL2.

Impurities are then injected into the region where source and drainregions (not shown) are to be formed by using an ion implantation methodand the word lines WL2 as a mask, thereby forming diffusion layers 301.A silicon nitride layer 210 is then formed by using a low pressure CVDmethod and portions of the silicon nitride layer 210 is removed by usinga RIE method, thereby forming side wall insulating films on the sidesurfaces of the word lines WL2.

A silicon nitride layer 211 is then formed on the silicon nitride layer210. A silicon oxide layer 212 is then formed on the silicon nitridelayer 211 by using a CVD method, and is removed so as to expose an uppersurface of the silicon nitride layer 211 by using a CMP method. Andthen, a silicon oxide layer 231 is formed by using a plasma CVD method.The silicon oxide layer 231 is then flattened by using a CMP method notso as to expose the upper surface of the silicon nitride layer 211 thatis formed above the gate electrode. In this case, the silicon oxidelayer 231 remains above the gate electrode. Therefore, when a contacthole 219 that will be mentioned later is formed, even if the contacthole 219 gets out of right position, the silicon oxide layer 231 that isformed above the gate electrode prevents the contact hole 219 fromreaching the gate electrode.

It is noted that the silicon oxide layer 231 may be flattened by using aCMP method so as to expose the upper surface of the silicon nitridelayer 211 that is formed above the gate electrode. In this case, aheight of the silicon oxide layer 231 can be lowered. In this result, wecan gat low etching ratio.

After that, a drain contact 202 a and a source line 203 will be formedas follows. As shown in FIG. 4, a photo resist layer (not shown) isformed on the silicon nitride layer 231. By using-a photolithographytechnique and a same photo mask, the photo resist layer is patternedinto a mask by which the drain contact 202 a and the source line 230 areto be formed. And then, portions of the silicon oxide layer 231 and thesilicon oxide layer 212 are removed by using a RIE method and thepatterned photo resist layer as a mask. The patterned photo resist layeris then removed.

Portions of the silicon nitride layer 211 are removed so as to exposethe upper surface of the semiconductor substrate 200 by using a RIEmethod. Ti layers 214 a, 214 b and W layers 214 a, 214 b are thenformed, thereby forming the drain contact 202 a and the source line 203.Portions of the Ti layers 214 a, 214 b and W layers 214 a, 214 b areremoved and flattened so as to expose an upper surface of the siliconoxide layer 231 by using a CMP method. It should be noted that thisembodiment of the present invention is different from the conventionalnon-volatile semiconductor memory device in that the drain contact andthe source line are formed simultaneously.

As shown in FIG. 5, a silicon oxide layer 213 is formed and a resistlayer (not shown) is then formed on the silicon oxide layer 213. Thephoto resist layer is patterned into a predetermined pattern by using aphotolithography technique and a same photo mask. Portions of thesilicon oxide layer 213 are then removed by using a RIE method and thepatterned photo resist layer as a mask, thereby simultaneously forming acontact hole 219 that is connected to the bit line 215 (See FIG. 1) andthe drain contact 202 a, and a contact hole 216 (shadowed) by which thesource line 203 is connected to another line (not shown) that is formedin a same layer as the bit line 215.

From this embodiment of the present invention, the same photo mask canbe used at the manufacturing step of the drain contact 202 a and thesource line 203. Moreover, the same mask can be used at themanufacturing step of the contact holes 219 and 216. Therefore, a heightof the drain contact 202 a is same as that of the source line 203, and aheight of the contact hole 219 is same as that of the contact hole 216.From this, the aspect ratio of the drain contact 202 a can be madelower, thereby resulting in preventing a poor conduction.

As stated above, in the conventional technique, a photo mask by whichthe drain contact is formed is different from a photo mask by which thesource line. On the other hand, in this embodiment of the presentinvention, the photo mask by which the drain contact 202 a is formed issame as photo mask by which the source line 203 is formed. Therefore, itcan enhance a precision of patterning, resulting in preventing a poorconduction as even downsizing progressed.

In this embodiment of the present invention, a NOR type non-volatilememory device is explained. However, it is noted that it can be an NANDtype non-volatile memory device.

We will explain about applications having an above-mentionedsemiconductor memory device. A memory card having the above mentionedsemiconductor memory device is shown in FIG. 9. As shown in FIG. 9, thesemiconductor memory device receives/outputs predetermined signals anddata from/to an external device (not shown).

A signal line (DAT), a command line enable signal line (CLE), an addressline enable signal line (ALE) and a ready/busy signal line (R/B) areconnected to the memory card having the above mentioned semiconductormemory device. The signal line (DAT) transfers data, address or commandsignals. The command line enable signal line (CLE) transfers a signalwhich indicates that a command signal is transferred on the signal line(DAT). The address line enable signal line (ALE) transfers a signalwhich indicates that an address signal is transferred on the signal line(DAT). The ready/busy signal line (R/B) transfers a signal whichindicates whether the memory device is ready or not. Another example ofa memory card is shown in FIG. 10. The memory card shown in FIG. 45differs from the memory card presented in FIG. 9 in that the memory cardincludes a controller which controls the semiconductor memory device andreceives/transfers predetermined signals from/to an external device (notshown).

The controller includes an interface unit (I/F), a micro processor unit(MPU), a buffer RAM and an error correction code unit (ECC). Theinterface unit (I/F) receives/outputs predetermined signals from/to anexternal device (not shown). The micro processor unit converts a logicaladdress into a physical address. The buffer RAM stores data temporarily.The error correction code unit generates an error correction code. And acommand signal line (CMD), a clock signal line (CLK) and a signal line(DAT) are connected to the memory card.

Although we explain about the memory cards as shown above, the number ofthe control signal lines, bit width of the signal line (DAT) and acircuit construction of the controller could be modified suitably.

Another application is shown in FIG. 11. A memory card holder to whichthe memory card is inserted, is shown in FIG. 11. And the card holder isconnected to electronic device (not shown). The card holder may have apart of the functions of the controller.

Another application is shown in FIG. 12. As shown in FIG. 12, the memorycard or the card holder to which the memory card is inserted, isinserted to a connecting apparatus. The connecting apparatus isconnected to a board via a connecting wire and an interface circuit. Theboard has a CPU (Central Processing Unit) and a bus.

Another application is shown in FIG. 13. As shown in FIG. 13, the memorycard or the card holder to which the memory card is inserted, isinserted to a connecting apparatus. The connecting apparatus isconnected to PC (Personal Computer) via connecting wire.

Another application is shown in FIGS. 14 and 15. As shown in FIG. 14, AnIC chip that includes the above-mentioned semiconductor memory device islocated on an IC card that is made of plastic or something like that.FIG. 15 shows a detail block diagram of the IC card and the IC chippresented in FIG. 14. The IC chip has a connecting terminal that isconfigured to connect to an external device (not shown), and a memorychip that includes the above-mentioned semiconductor memory device, aROM, a RAM, and a CPU. The CPU contains a calculation section and acontrol section that is configured to connect to the semiconductormemory device.

Additional advantages and modifications will readily occur to thoseskilled in the art. Therefore, the invention in its broader aspects isnot limited to the specific details and representative embodiments shownand described herein. Accordingly, various modifications may be madewithout departing from the spirit or scope of the general inventiveconcept as defined by the appended and their equivalents.

1-30. (canceled)
 31. A method of manufacturing a semiconductor memorydevice having a gate electrode and a diffusion layer, comprising:forming a plurality of memory cells each of which including the gateelectrode and the diffusion layer; forming a first interlayer insulatingfilm among the gate electrodes of the plurality of the memory cells;forming a first contact hole and a second contact hole, the firstcontact hole reaches one of the diffusion layers of the plurality of thememory cells and the second contact hole reaches at least two of thediffusion layers of the plurality of the memory cells; forming a firstconductive layer in the first contact hole and a second conductive layerin the second contact hole; forming a second interlayer insulating filmon the first interlayer insulating film; forming a third contact hole inthe second interlayer insulating film; forming a third conductive layerin the third contact hole, the third conductive layer connected to thefirst conductive layer; and forming a bit line connected to the thirdconductive layer.
 32. The method of manufacturing a semiconductor memorydevice having a gate electrode and a diffusion layer according to claim31, a height of the first conductive layers is same as that of thesecond conductive layer.
 33. The method of manufacturing a semiconductormemory device having a gate electrode and a diffusion layer according toclaim 31, the forming of the first contact layer is steps of forming afirst conductive film in the first contact hole, and forming a secondconductive film on the first conductive film in the first contact hole.34. The method of manufacturing a semiconductor memory device having agate electrode and a diffusion layer according to claim 31, the formingof the second contact layer is steps of a first conductive film in thefirst contact hole, and forming a second conductive film on the firstconductive film in the first contact hole.
 35. The method ofmanufacturing a semiconductor memory device having a gate electrode anda diffusion layer according to claim 31, further comprising, forming aninsulating film to cover the gate electrodes of the plurality of thememory cells after forming the plurality of memory cells.
 36. The methodof manufacturing a semiconductor memory device having a gate electrodeand a diffusion layer according to claim 35, the insulating film is asilicon nitride.
 37. The method of manufacturing a semiconductor memorydevice having a gate electrode and a diffusion layer according to claim31, the forming of a first interlayer insulating film among the gateelectrodes comprises steps of forming the first interlayer insulatingfilm, and removing portion of the first interlayer insulating film so asto expose an upper surface of the insulating film that is formed tocover the gate electrode.
 38. The method of manufacturing asemiconductor memory device having a gate electrode and a diffusionlayer according to claim 31, the forming of a first interlayerinsulating film among the gate electrodes comprises steps of forming thefirst interlayer insulating film, and removing portion of the firstinterlayer insulating film so as to keep the first interlayer insulatingfilm above the gate electrode.
 39. A method of manufacturing asemiconductor memory device having a gate electrode and a diffusionlayer, comprising: forming a plurality of memory cells each of whichincluding the gate electrode and the diffusion layer; forming a firstinterlayer insulating film among the gate electrodes of the plurality ofthe memory cells; removing portions of the first interlayer insulatingfilm and forming a first contact hole and a second contact hole, thefirst contact hole reaches one of the diffusion layers of the pluralityof the memory cells and the second contact hole reaches at least two ofthe diffusion layers of the plurality of the memory cells; forming afirst conductive layer in the first contact hole and a second conductivelayer in the second contact hole; forming a second interlayer insulatingfilm on the first interlayer insulating film, the first conductivelayer, and the second conductive layer; removing a portion of the secondinterlayer insulting film and forming a third contact hole; forming athird conductive layer in the third contact hole, the third conductivelayer connected to the first conductive layer; and forming a bit lineconnected to the third conductive layer.
 40. The method of manufacturinga semiconductor memory device having a gate electrode and a diffusionlayer according to claim 39, the forming of the first contact layer issteps of forming a first conductive film in the first contact hole, andforming a second conductive film on the first conductive film in thefirst contact hole.
 41. The method of manufacturing a semiconductormemory device having a gate electrode and a diffusion layer according toclaim 39, the forming of the second contact layer is steps of forming afirst conductive film in the first contact hole, and forming a secondconductive film on the first conductive film in the first contact hole.42. The method of manufacturing a semiconductor memory device having agate electrode and a diffusion layer according to claim 39, furthercomprising, forming an insulating film to cover the gate electrodes ofthe plurality of the memory cells after forming the plurality of memorycells.
 43. The method of manufacturing a semiconductor memory devicehaving a gate electrode and a diffusion layer according to claim 42, theinsulating film is a silicon nitride.
 44. The method of manufacturing asemiconductor memory device having a gate electrode and a diffusionlayer according to claim 39, the forming of a first interlayerinsulating film among the gate electrodes comprises steps of forming thefirst interlayer insulating film, and removing portion of the firstinterlayer insulating film so as to expose an upper surface of theinsulating film that is formed to cover the gate electrode.
 45. Themethod of manufacturing a semiconductor memory device having a gateelectrode and a diffusion layer according to claim 39, the forming of afirst interlayer insulating film among the gate electrodes comprisessteps of forming the first interlayer insulating film, and removingportion of the first interlayer insulating film so as to keep the firstinterlayer insulating film above the gate electrode.
 46. The method ofmanufacturing a semiconductor memory device having a gate electrode anda diffusion layer according to claim 39, a height of the firstconductive layers is same as that of the second conductive layer.